Embodiments of the invention relate generally to integrated circuit packages and, more particularly, to adhesive placement within the integrated circuit package.
As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminated-based ball grid array (BGA) packaging and eventually to chip scale packaging (CSP). Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
A standard CSP manufacturing process typically begins by mounting a dielectric substrate or flex layer to a frame that stabilizes the substrate during the manufacturing process. An adhesive is dispensed in liquid form onto the surface of the dielectric substrate and the frame is spun rapidly to spread the liquid adhesive to a uniform thickness across the entire surface of the dielectric. Next, one or more dies are positioned active side down into the adhesive and the adhesive is cured. A plurality of re-distribution layers are then deposited onto the dielectric substrate and patterned to form a thin-film metal re-routing and interconnection system, with eight or more re-distribution layers being common. The re-distribution layers are typically formed from a benzocyclobutene (BCB) or polyimide material, for example, and applied via a spin-on or lamination application process. The electrical connection between the laminate re-distribution layers and the die(s) form an input/output (I/O) system to and from the die(s).
Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. As IC packages become thinner, the adhesive layer may cause the IC package to warp or otherwise become distorted as a result of uneven stress distributions on the top and bottom surfaces of the dielectric layer. Further, in order to manufacture smaller and more complex multi-chip IC packages, dies must be positioned more closely together and with great precision on the dielectric. However, the adhesive layer that couples the dies to the dielectric can make precise alignment of closely spaced dies difficult. For example, when two or more dies are positioned in close proximity to one another on the dielectric, the dies have a tendency to “swim” or move out of the desired position during the adhesive curing process. In addition to merely moving out of the desired position, closely spaced dies may be attracted to one another while the adhesive is curing, a phenomenon that may cause the undesired result of dies touching or becoming stuck to one another in the final chip package.
Accordingly, there is a need for a method of chip package fabrication that minimizes the warpage and distortion that can be caused by the adhesive layer and that allows for closer die spacing and precise die alignment in the IC package. There is a further need for the fabrication method to be readily incorporated into an assembly process, minimize processing time, and provide for a low cost assembly.